Semiconductor integrated circuits typically include a memory circuit including a storage element such as a ROM, a flash memory, an SRAM or a DRAM, and a logic circuit including sequential circuits such as flip-flops and combination circuits. For maintenance and enhancement of the product quality of such semiconductor integrated circuits, it is important to detect an irregular delay in the logic circuit or the memory circuit as a delay fault. For example, for a test for detecting a delay fault in the logic circuit, a scan test is known, and, for a test for detecting a delay fault in the memory circuit, a memory BIST (built-in self-test) is known.
In a scan test, a scan path, which is provided in advance in a logic circuit of a semiconductor integrated circuit, is used. In other words, in a scan test, a testing apparatus sets sequential circuits in an output control circuit to a predetermined state via the scan path. The predetermined state is set so that upon a state of sequential circuits disposed so as to precede a combination circuit is transmitted to sequential circuits disposed so as to follow the combination circuit, the state of the following sequential circuits transitions. The testing apparatus sets the sequential circuits to the predetermined state and then makes the combination circuit operate at a frequency of actual operation, transmits the state of the sequential circuits disposed so as to precede the combination circuit to the sequential circuits disposed so as to following the combination circuit via the combination circuit, and further extracts the state of the following sequential circuits via the scan path, and determines whether or not the extracted state of the sequential circuits corresponds to a predetermined expected value, whereby the testing apparatus detects a delay fault in the logic circuit.
On the other hand, in a memory BIST, a dedicated circuit, which is provided in advance in a semiconductor integrated circuit, is used. In other words, in a memory BIST, a testing apparatus writes test data into a memory circuit at an actual operation speed using the dedicated circuit, and then reads the written test data and determines whether or not the read test data corresponds to a predetermined expected value, thereby detecting a delay fault in the memory circuit.
However, in a test specialized for delay fault detection in either a logic circuit or a memory circuit such as stated above, no delay fault in a path from the logic circuit to the memory circuit and a path from the memory circuit to the logic circuit can be detected. In other words, although in order to detect a delay fault in the path from the logic circuit to the memory circuit or the path from the memory circuit to the logic circuit, it is necessary to make these circuits operate simultaneously during a test, the test is designed so as to make only a specific one of the circuits operate, no consideration of making two circuits operate simultaneously has been made.
Therefore, for example, as disclosed in Japanese Patent Laid-Open No. 2010-197149, a semiconductor apparatus for detecting a delay fault in a path from a logic circuit to a memory circuit has been proposed. In other words, in the semiconductor apparatus disclosed in Japanese Patent Laid-Open No, 2010-197149, an output from an input-side test-specific logical circuit disposed so as to precede a memory macro is temporarily loaded into a scan flip-flop and an output from the scan flip-flop is output to the memory macro, enabling detection of a delay fault in a path from the scan flip-flop to the memory macro.
However, as described above, in the semiconductor apparatus disclosed in Japanese Patent Laid-Open No. 2010-197149, an output of the input-side test-specific logical circuit preceding the memory macro is temporarily loaded into the scan flip-flop and the loaded data is output from the scan flip-flop to the memory macro, and thus no delay fault in a path from a downstream-most combination circuit in an input-side user logic circuit preceding the memory macro to the memory macro still can be detected, which is insufficient for delay fault detection in a part of connection between a logic circuit and a memory circuit in a semiconductor integrated circuit.
Therefore, an object of the present invention is to provide a testing circuit enabling delay fault detection in a path from a downstream-most combination circuit in a preceding logic circuit to a memory circuit and a path from the memory circuit to a following combination circuit in a semiconductor integrated circuit.